As digital electronic processing systems trend toward higher operating frequencies and smaller device geometries, power management has become increasingly important to prevent thermal overload while maintaining system performance and prolonging battery life in portable systems.
The two principal sources of power dissipation in digital logic circuits are static power dissipation and dynamic power dissipation. Static power dissipation is dependent on temperature, device technology and processing variables, and is composed primarily of leakage currents. Dynamic power dissipation is the predominant loss factor in digital circuitry and is proportional to the operating clock frequency, the square of the operating voltage and the capacitive load. Capacitive load is highly dependent on device technology and processing variables, so most approaches to dynamic power management focus on frequency and voltage control.
One conventional approach to power management halts the processing system to adjust core clock frequencies and voltages, during which time the processor does not execute operating system code or application code, and then restarts the system after the new frequencies and voltages have stabilized.
Another conventional approach to power management changes the clock frequency of a processor while the processor is operating, but requires the frequency changes to be made in small increments to avoid processing errors that large frequency steps would cause. As a result, this approach may require a significant time period to achieve a desired operating frequency.
Yet another conventional approach to power management employs a fixed relationship between voltage and frequency, either through a lookup table or by use of a frequency to voltage converter. In this approach, a frequency increase is always preceded by a voltage increase and a frequency decrease always precedes a voltage decrease. In addition, a frequency increase is delayed while the voltage is ramped up to a corresponding voltage. The new frequency and voltage are not scaled independently, and the new operating point may not be optimum with respect to an application's processing demand.
In some conventional data processing systems, processors within the systems execute software at the operating system (OS) level to perform power management. The processor core of a typical data processing system has a fixed external frequency reference that is multiplied up internally to a higher frequency. The processor may adjust the internal switching frequency of the processor core by either adjusting a phase locked loop (PLL) multiplication factor, adjusting an internal clock divider, or a combination thereof. The processor may estimate a preferred switching frequency by monitoring the current tasks and the pending task deadlines. However, the processor has to devote some processing overhead to execute the software. As such, this approach is an inefficient way to extract the maximum amount of power savings. In addition, the software is executed in a non-realtime OS, and thus, may add more latency and reduce the amount of power savings.
Furthermore, some conventional processors execute software to make all decisions on how and when to adjust the voltages and clocks in the system. In many cases, the software executed by the conventional processors involves mathematical routines (e.g., division, integration, minimization, etc.). It is generally difficult to implement these routines on hardware because of the large gate count and high power requirement.
Because the majority of processors do not incorporate internal adjustable voltage regulators to optimize the core voltage, it is more difficult to implement dynamic voltage scaling (DVS) of the processor core than dynamic clock scaling. Therefore, many conventional designs that incorporate dynamic frequency scaling (DFS) adopt a fixed “worst-case” core voltage, instead of implementing DVS. However, in designs that do incorporate DVS at the processor level, the typical approach is to interface a power management unit (PMU) to the processor using a master/slave serial bus. With this configuration, the processor acting as the master communicates the desired core voltage data to the PMU whenever the processor has to adjust the core voltage. The serial nature of this approach may cause undesirable latency in DVS, and in turn, may add undesirable latency to DFS. This latency in DVS and DFS reduces power savings by delaying the transition of the processor core to a lower power mode and decreases processor performance by delaying the transition of the processor core to a higher power mode when demanded by the pending tasks.
One common conventional approach to implement DVS is to use a look-up table in software on the processor. For every clock frequency that may be used in DFS, a minimum “worst-case” core voltage is calculated. Therefore, whenever the DFS software in the processor calculates a new operating frequency, the respective core voltage is retrieved from the look-up table and communicated to the external PMU as necessary through software. This approach may generally be implemented on processors with internal clock scaling circuitry.
Another conventional approach to implement DVS is to incorporate a specialized hardware block on the processor that is capable of determining the preferred core voltage. This approach has an advantage over the look-up table approach because additional parameters can be considered, such as process, temperature, well biasing, etc. However, one major disadvantage in this approach is that it is processor dependent, and thus, may only be implemented on a small subset of available processors. Furthermore, this approach does little to address the latency issue because the processor still uses a serial bus to communicate voltage changes to the PMU.